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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Features
* Meets jitter requirements for AT&T TR62411 Stratum 4 and Stratum 4 Enhanced for DS1 interfaces, and for ETSI ETS300 011 for E1 interfaces * Provides C1.5, C3, C2, C4, C8 and C16 output clock signals * Provides 3 kinds of 8kHz framing signals * Selectable 1.544MHz, 2.084MHz or 8kHz input reference signals * Operates in either Normal or Free-Run states * Enhanced in jitter and duty cycle comparing with PT7A4401B * Package: 28-pin PLCC (PT7A4401CJ)
Introduction
PT7A4401C is functionally enhanced version of PT7A4401B. It has better jitter performance and C16 whose output duty cycle is independent of 20MHz master clock. The PT7A4401C employs a digital phase-locked loop (DPLL) to provide timing and synchronizing signals for multitrunk T1 and E1 primary rate transmission links. It generates the ST-BUS clock and framing signals that are phase-locked to input reference signals of either 2.048MHz, 1.544MHz or 8kHz. The PT7A4401C is compliant with AT&T TR62411 Stratum 4 and Stratum 4 Enhanced, and ETSI ETS 300 011. It meets the requirements for jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase slope, etc.
Applications
* Synchronization and timing control for multitrunk T1 and E1 systems * ST-BUS clock and frame pulse sources
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Contents
Contents Page
Features ............................................................................................................................................... 1 Applications ........................................................................................................................................ 1 Introduction ......................................................................................................................................... 1 Block Diagram .................................................................................................................................... 3 Pin Information ................................................................................................................................... 4 Pin Assignment .......................................................................................................................... 4 Pin Configuration ...................................................................................................................... 4 Pin Description .......................................................................................................................... 5 Functional Description ........................................................................................................................ 6 Overall Operation ...................................................................................................................... 6 States of Operation .................................................................................................................... 7 Applications Information ........................................................................................................... 8 Detailed Specifications ...................................................................................................................... 10 Definition of Critical Performance Specifications .................................................................... 10 Absolute Maximum Ratings .................................................................................................... 11 Recommended Operating Conditions ...................................................................................... 11 DC Electrical and Power Supply Characteristics ..................................................................... 12 AC Electrical Characteristics ................................................................................................... 13 Mechanical Specifications ....................................................................................................... 25 Ordering Information ........................................................................................................................ 26 Notes ................................................................................................................................................. 27
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Block Diagram
Figure 1. Block Digram
VCC GND
Output Circuit REF Phase Detector Limiter & Loop Filter DCO1 T1 Divider C1.5 C3
C2 E1 Input Impairment Monitor State Machine DCO2 Divider C4 C8 C16 F0 F8 F16 OSCi OSCo Master Clock Feedback Frequency Select MUX
RST
MS
FS1
FS2
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p s Chip Clock Power & Ground Clock and Framing Output Control Signals Reference Input
Symb ols OSCi, OSCo VCC, GND C1.5, C3, C2, C4, C8, C16, F0, F8, F16 MS, FS1, FS2, RST REF
F u n ct ion s Clock Power Clock and Framing Signals Control Reference Clock
Pin Configuration
Figure 2. Pin Configuration
GND
RST
REF
FS1
43 VCC OSCo OSCi F16 F0 F8 C1.5 5 6 7 8 9 10 11
2 1 28 27 26 25 24 23 28-Pin PLCC 22 21 20 19 NU NU MS NU NU NC NU
12 13 14 15 16 17 18 GND C16 VCC C3 C2 C4 C8
Top View
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NU
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Pin Description
Table 2. Pin Description
P in
1, 15 2, 3, 19, 21, 22, 24, 25 4 5, 18 6 7
Na m e
GND NU REF Vcc OSCo OSCi
Typ e
Ground I I Power O I G r ou n d (0V)
Descr ip t ion
Not Used (should be connected to ground) R efer en ce I n p u t (T T L com p a t ib le): Input reference signals Power Su p p ly (+5V) O scilla t or Ma st er C lock O u t p u t (C MO S): Output of 20MHz master clock O scilla t or M a st er C lock I n p u t (C M O S): Input of 20MHz master clock (can be connected directly to a clock source) F r a m e P u lse O u t p u t (C MO S C om p a t ib le): 8kHz framing output pulse that indicates the start of the ST-BUS frame. The pulse width is based upon the period of the 16.384MHz synchronization clock. F r a m e P u lse O u t p u t (C MO S C om p a t ib le): 8kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096MHz synchronization clock. F r a m e P u lse O u t p u t (C MO S C om p a t ib le): 8kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192MHz synchronization clock. 1.544MH z C lock (C MO S C om p a t ib le) 3.088MH z C lock (C MO S C om p a t ib le) 2.048MH z C lock (C MO S C om p a t ib le) 4.096MH z C lock (C MO S C om p a t ib le) 8.192MH z C lock (C MO S C om p a t ib le) 16.384MH z C lock (C MO S C om p a t ib le) Not C on n ect ed : Make no connection to this pin. Mod e Select (T T L C om p a t ib le): This input selects the operation mode of the device, i.e., Normal or Freerun. Refer to Table 4. F r eq u en cy Select 2 (T T L C om p a t ib le): This input, together with FS1, selects the frequency of the input reference signal, either 8kHz, 1.544MHz or 2.048MHz. Refer to Table 3. F r eq u en cy Select 1 (T T L C om p a t ib le): Refer to the pin description of FS2. R eset (C MO S I n p u t Sch m it t Tr igger ): Reset the device when at low level. The reset is needed when power-up or when frequency select input change to ensure proper operation. The time constant for a power-up reset circuit must be a min. of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a min. of 300 ns to reset the device. When RST at low level, all outputs are fixed at HIGH.
8
F16
O
9
F0
O
10
F8
O
11 12 13 14 16 17 20 23
C1.5 C3 C2 C4 C8 C16 NC MS
O O O O O O O I
26 27
FS2 FS1
I I
28
RST
I
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Functional Description
Overall Operation
The PT7A4401C is a multitrunk synchronizer that provides the clock and frame signals for T1 and E1 primary rate digital transmission links. It basically consists of the Master Clock Circuit, Digital PhaseLocked Loop (DPLL), Input Impairment Monitor and Output Circuit. The DPLL circuit is employed to provide synchronization of the output signals. Referring to the block diagram on Page 3, the detailed functions of the PT7A4401C are described as follows. Master Clock As its master clock, the PT7A4401C uses either an external clock source or an external crystal and a few discrete components with its internal oscillator. Major Digital Phase-Locked Loop (DPLL) Block The major DPLL blocks are the Phase Detector, Limiter, Loop Filter, and Digitally Controlled Oscillators (DCO1 and DCO2). The input signal is sent to the Phase Detector for comparison with the feedback Signal from the Feedback Frequency Select MUX. An error signal corresponding to their instantaneous phase difference is produced and sent to the Limiter. The Limiter amplifies this error signal to ensure that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125s. This performance easily meets the maximum phase slope of 7.6ns per 125s or 81ns per 1.326ms specified by AT&T TR62411. The Loop Filter is a 1.9Hz low pass filter for all three reference frequency selections: 8kHz, 1.544MHz and 2.048MHz. This filter ensures that the jitter transfer requirements in ETS 300011 and AT&T TR62411 are met. The Error Signal, after being limited and filtered, is sent to two Digitally Controlled variable frequency Oscillators (DCO1 and DCO2). Based upon the processed error value, the DCOs will generate the corresponding digital output signals to the Output Circuit to produce 12.352MHz and 16.384MHz signals.
The DCO synchronization method depends upon the PT7A4401C operating state, as follows: In Normal state, each DCO generates an output signal which is frequency and phase locked to the input reference signal. In Auto-Holdover state, each DCO generates an output signal whose frequency is equal to what it was for a 30ms period shortly before the end of the last Normal State. In Free-Run state, the DCOs are free running with an accuracy equal to the accuracy of the OSCi 20MHz source. Output Circuit Signals from the two DCOs are sent to the Output Circuit to generate two clock signals, 12.352MHz and 16.384MHz, which are divided in the T1 and E1 Dividers respectively to provide needed clock and frame signals. The T1 Divider uses the 12.352MHz signal to generate two clock signals, C1.5 and C3. They have a nominal 50% duty cycle. The E1 Divider uses the 16.384MHz signal to generate four clock signals and three frame signals, i.e., C2, C4, C8, C16, F0, F8 and F16. The frame signals are generated directly from the C16 signal. The C2, C4 and C8 signals have a nominal 50% duty cycle, and C16's duty cycle is about 50% if the master clock has a 50% duty cycle. All the frame and clock outputs are locked to each other for all operating states. They have limited driving capability and should be buffered when driving high capacitance loads. Feedback Frequency Selection MUX The feedback frequency is selected by FS1 and FS2 (as shown in Table 3) to match the particular incoming reference frequency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must be performed after every frequency select input change. Input Impairment Monitor This circuit monitors the input signal to the DPLL and automatically enables Auto-Holdover state when the incoming signal is completely lost, or if its frequency is outside the Autoholdover capture range (either a small or large amount). When the incoming signal returns to normal, the DPLL will be returned to Normal State.
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Table 3. Input Frequency Selection
States of Operation
Typically, the PT7A4401C operates in either the Normal or Free-Run state. However, when the input signal is temporarily missing or its frequency is temporarily out of specification, it operates in Auto-Holdover State (Refer to Table 7). Normal State In Normal State, the output signals of the PT7A4401C are synchronized with the input reference signal by the DPLL. Free-Run State Typically, the Free-Run State is used immediately following system power-up before network synchronization is achieved, or when a master clock is otherwise required. In Free-Run State, the outputs of the PT7A4401C are uncorrelated with the input reference signal (and the stored information concerning the output reference signals). Instead, these output signals are based solely on the master clock frequency (OSCi). Auto-Holdover State The Auto-Holdover State will be automatically initiated when incoming reference signal disappears or its frequency moves outside the Auto-holdover capture range (Table 7), by either a small or large amount. In Auto-Holdover State, the PT7A4401C output signals are not synchronized with the external input reference signal. Instead, they are generated by using the information stored 30 ms to 60ms before the incoming reference signal became unusable. While in Normal State, a numerical value related to the output reference frequency is stored alternately in two memory locations every 30ms. Whenever the device is switched into AutoHoldover State, the value in memory between 30ms and 60ms is used to set the output frequency of the device.
F S2 0 0 1 1
F S1 0 1 0 1
I n p u t F r eq u en cy Reserved 8kHz 1.544MHz 2.048MHz
State Machine If the value of MS is 1, the "Free-Run" state of operation is forced. If the value of MS is 0, the state of operation is either "Normal" or "Auto-Holdover", depending upon the state of the Input Impairment Monitor. See Table 4. Table 4. Operation State Selection
MS MS 0 1
O p er a t ion St a t e Normal Freerun
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Applications Information
Master Clock The PT7A4401C uses either an external clock source or an external crystal and a few passive components with its internal oscillator as the master timing source. In Free-Run State, the frequency tolerance of the PT7A4401C output clocks are equal to the frequency tolerance of the timing source. In a given application, if an accurate Free-Run State is not required, the tolerance of the master timing source may be 100ppm. If required, the tolerance must be no worse than 32 ppm. The capture range of PT7A4401C must also be considered when deciding the accuracy of the master timing source. The sum of the accuracy of the master timing source and the capture range of the PT7A4401C will always equal 230ppm. For example, if the master timing source is 100ppm, the capture range will be 130ppm. * Clock Oscillator If using an external clock source, its output pin should be connected directly (not AC coupled) to the OSCi pin of the PT7A4401C, and the OSCo pin can be left open as shown in Figure 3 or connected as an output pin.
When selecting the clock oscillator, following specifications should be considered. They are - absolute frequency - frequency change over temperature - output rise and fall time - output level - duty cycle * Crystal Oscillator If a crystal and passive components operating together with the PT7A4401C oscillator are selected as the master timing source, they should be connected as shown in Figure 4. It should be possible to adjust the trimmer capacitor so that the frequency is well within the 32 ppm tolerance; however, only the proper specification of components will insure this tolerance over the necessary temperature range.
Figure 4. Crystal Oscillator Connection
PT7A4401C 20MHz OSCi
1M
56pF
39pF
3-50pF
Figure 3. Clock Oscillator Connection
PT7A4401C +5V OSCi +5V 20MHz OUT GND OSCo 100
0.1F
The crystal specification is as follows: - Frequency: - Tolerance: - Oscillation Mode: - Resonance Mode: - Load Capacitance: - Maximum Series Resistance: - pproximate Drive Level: 20MHz as required Fundamental Parallel 32pF 35 1mW
OSCo No Connection
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Reset Circuit A simple power-up reset circuit with about a 50s reset active (low) time is shown in Figure 5. Resistor RP is used for protection only. The reset time is not critical but should be greater than 300ns.
Power Supply Decoupling The PT7A4401C has two VCC pins and two GND pins. Power decoupling capacitors should be included as shown in Figure 6.
Figure 6. Power Supply Decoupling Figure 5. Power-up Reset Circuit
PT7A4401C C1 0.1F
+5V
R 10k RST RP 1k C 10nF
+
18
15
PT7A4401C
5 1 +
C2 0.1F
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Detailed Specifications
Definitions of Critical Performance Specifications
Intrinsic Jitter: Intrinsic jitter is the jitter produced by the synchronizing circuit. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode--such as free running or auto-holdover--by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. Jitter Tolerance: Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is present on its reference. The applicable standard specifies how much jitter to apply to the reference when testing for jitter tolerance. Jitter Transfer: Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device with respect to a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standard. Its 3 possible input frequencies and 9 outputs gives the PT7A4401C 27 possible jitter transfer combinations. However, only three cases of the jitter transfer specifications are given in the AC Electrical Characteristics; as the remaining combinations can be derived from them. For the PT7A4401C, jitter attenuation is determined by the internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125s. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125s. It should be noted that 1UI at 1.544MHz (644ns) is not equal to 1UI at 2.048MHz (488ns). A transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. Example - When the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB, the T1 and E1 output jitter can be calculated as follows: JT1o
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based upon the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. As intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Frequency Accuracy: Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is operating in a free running mode (not locked to an external reference). For the PT7A4401C, Free-Run accuracy is equal to the Master Clock (OSCi) accuracy. Auto-Holdover Accuracy: Auto-Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the PT7A4401C the storage value is determined while the device is in Normal State and locked to an external reference signal. The absolute Master Clock (OSCi) accuracy of the PT7A4401C does not affect Auto-Holdover accuracy, but the change in OSCi accuracy while in Auto-Holdover State does. Lock Range: If the PT7A4401C DPLL is already in a state of synchronization ("lock") with the incoming reference signal, it is able to track this signal to maintain lock as its frequency varies over a certain range, called the Lock Range. The size of Lock Range is related to the range of the Digitally Controlled Oscillators and is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock results in a Lock Range of 198ppm. Capture Range: If the PT7A4401C DPLL is not at present in a state of synchronization (lock) with the incoming reference signal, it is able to initiate (acquire) lock only if the signal's frequency is within a certain range, called the Capture Range. For any PLL, no portion of the Capture Range can fall outside the Lock Range, and, in general, the Capture Range is more narrow than the Lock Range. However, owing to the design of its Phase Detector, the PT7A4401C's Capture Range is equal to its Lock Range. Phase Slope: Phase slope is measured in seconds per second and is defined as the rate at which a given signal changes phase with respect to an ideal signal of constant frequency. The given signal is typically the output signal. The ideal signal has a constant frequency that is nominally equal in value to that of the final output signal or final input signal.
( -18 ) ( -A ) = JT1i x 10 2 0 = 20 x 10 2 0 = 2.5UI
JE1o = JT1o x ( 1UIT1) = JT1o x ( 644ns ) = 3.3UI 1UIE1 488ns
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Absolute Maximum Ratings
Storage Temperature ...................................................... -65oC to +150oC Ambient Temperature with Power Applied ...................... -40oC to +85oC Supply Voltage to Ground Potential (Inputs & VCC Only) ...... -0.3 to 7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.3 to 7.0V DC Input Voltage .................................................................. -0.3 to 7.0V DC Output Current ...................................................................... 120mA Power Dissipation ....................................................................... 900mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Sym VCC TA Descr ip t ion Supply Voltage Operating Temperature Test C on d it ion s Min 4.5 -40 Typ 5.0 25 Ma x 5.5 85 Un it s V
o
Over Recommended Operating Conditions
C
Note: Typical figures are at 25oC and are for design aid only; not production tested.
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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DC Electrical and Power Supply Characteristics
Table 6. DC Electrical and Power Supply Characteristics
Sym ICCO ICC
Descr ip t ion Quiescent Power Supply Current
Test C on d it ion s OSCi = 0V, Note 2
Min
Typ
Ma x 500 50
Un it s A mA mA V
Supply Current ICC VIH VIL VCIH VCIL VSIH VSIL VHYS IIL VOH VOL TTL HIGH Input Voltage-All pins except OSCi, RST TTL LOW Input Voltage-All pins except OSCi, RST CMOS HIGH Input VoltageOSCi pin CMOS LOW Input VoltageOSCi pin Schmitt HIGH Input VoltageRST pins Schmitt LOW Input VoltageRST pins Schmitt Hysteresis VoltageRST pins Input Leakage Current HIGH Output Voltage LOW Output Voltage VI = VCC or 0V IOH = 4mA IOL = 4mA 2.4 0.8 1.0 10 3.6 1.5 0.7VCC 0.3VCC OSCi = Crystal, Note 2 2.0 0.8 60
V V V V V V A V V
Note: 1. VCC = 5V, 2. MS = VCC (Freerun), FS1 = VCC, FS2 = GND, REF = GND, other inputs connected to GND. 3. All outputs are unloaded except for VOH and VOL measurement.
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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AC Electrical Characteristics
Performance Table 7. Performance
Sym Descr ip t ion 0ppm Freerun State Accuracy with OSCi at: 32ppm 100ppm 0ppm Capture Range With OSCi at: 32ppm 100ppm Phase Lock Time Output Phase Slope 1, 4-12 1-12, 25 1, 4-6 3 Test C on d it ion s* Min 0 -32 -100 -190 -158 -90 Typ Ma x 0 +32 +100 +230 +198 +130 30 45 Un it s ppm ppm ppm ppm ppm ppm s s/s
* Refer to the Test Conditions on Page 24 for details.
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Voltage Levels for Timing Parameter Measurement Table 8. Voltage Levels for Timing Parameter Measurement
Sym VT VHM VLM
Descr ip t ion Threshold Voltage Rising and Falling Threshold Voltage High Rising and Falling Threshold Voltage Low
Sch mit t (for R ST ) 1.5 2.4 0.8
TTL 1.5 2.0 0.8
CMOS (for O SC i) 0.5VCC 0.7VCC 0.3VCC
Un it s V V V
Figure 7. Voltage Levels for Timing Parameter Measurement
Timing Reference Points Signal VHM VT VLM
tIF/tOF
tIR/tOR
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Timing Characteristics Table 9. Timing Characteristics
Sym tRW tIR/tIF tR8D tR15D tR2D tF0D tF16D tC15D tC3D tC2D tC4D tC8D tC16D tC15W tC3W tC2W tC4W tC8W Descr ip t ion Reference Input Pulse Width High or Low 1, 4-9, 37 Reference Input Rising or Falling Time 8kHz Reference Input to F8 Delay 1.544MHz Reference Input to F8 Delay 2.048MHz Reference Input to F8 Delay F8 to F0 Delay F8 to F16 Delay F8 to C1.5 Delay F8 to C3 Delay F8 to C2 Delay F8 to C4 Delay F8 to C8 Delay F8 to C16 Delay C1.5 Pulse Width High or Low C3 Pulse Width High or Low C2 Pulse Width High or Low C4 Pulse Width High or Low C8 Pulse Width High or Low 1-12, 19, 37 1-12, 19, 37 1-12, 19 1, 4-12, 19, 21, 36 -28 337 217 110 19 -45 -46 -10 -10 -10 -10 309 149 230 111 52 10 -1 363 238 134 44 -31 -31 5 5 5 5 339 175 258 133 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test C on d it ion s* Min 100 Typ Ma x Un it s ns
* Refer to the Test Conditions on Page 24 for details. Note: 1. Typical figures are at 25oC and are for design aid only; not production tested. 2. The maximum and minimum timing is measured under recommended temperature conditions and power supplies. 3. TTL voltage levels are used for timing parameter measurement.
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Table 9. Timing Characteristics (Continued)
Sym tC16WL tF0WL tF8WH tF16WL tORF tS tH Descr ip t ion C16 Pulse Width Low F0 Pulse Width Low F8 Pulse Width High F16 Pulse Width Low Output Clock and Frame Pulse Rising or Falling Time Input Controls Setup Time Input Controls Hold Time 1-12, 19, 37 9 100 100 ns ns ns Test C on d it ion s* 1-12, 19 Min 26 230 111 52 Typ Ma x 37 258 133 70 Un it s ns ns ns ns
* Refer to the Test Conditions on Page 24 for details. Note: 1. Typical figures are at 25oC and are for design aid only; not production tested. 2. The maximum and minimum timing is measured under recommended temperature conditions and power supplies. 3. TTL voltage levels are used for timing parameter measurement.
Figure 8. Setup and Hold Timing of Input Controls
F8
VT
tS
MS
tH
VT
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Figure 9. Timing Information for PT7A4401C
t R 8D
RE F 8kH z VT
t R 15 D
RE F 1.544M Hz
tRW
tRW
VT
t R 2D
RE F 2.048M Hz
tRW
VT
F8
VT
Note: Input to output delay values are valid after a RST with no further state changes.
Figure 10. Output Timing
tF8W H
F8 VT
tF0D tF0W L
F0 VT
tF16D
F16
tF16W L tC 16W L tC 16D
VT
C16
VT
tC 8W
C8
tC 8W
tC 8D
VT
tC 4W
C4
tC 4D tC 4W tC 2D
VT
C2
tC 2W
VT
tC 3D tC 3W
C3
tC 3W
VT
tC 15W
C 1 .5
tC 15D
VT
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Intrinsic Jitter Unfiltered Table 10. Intrinsic Jitter Unfiltered
Sym
Descr ip t ion Instrinsic Jitter at F0 (8kHz) Instrinsic Jitter at F8 (8kHz) Instrinsic Jitter at F16 (8kHz) Instrinsic Jitter at C1.5 (1.544MHz) Instrinsic Jitter at C2 (2.048MHz) Instrinsic Jitter at C3 (3.088MHz) Instrinsic Jitter at C4 (4.096MHz) Instrinsic Jitter at C8 (8.192MHz) Instrinsic Jitter at C16 (16.384MHz)
Test C on d it ion s*
Min
Typ 0.0001
Ma x 0.0002 0.0002 0.0002 0.030 0.040 0.060 0.080 0.16 0.32
Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
1-12, 19-22, 26, 33
0.0001 0.0001
1-12, 19-22, 27, 33 1-12, 19-22, 28, 33 1-12, 19-22, 29, 33 1-12, 19-22, 30, 33 1-12, 19-22, 31, 33 1-12, 19-22, 32, 33
0.016 0.020 0.032 0.047 0.09 0.18
* Refer to the Test Conditions on Page 24 for details.
C1.5 (1.544MHz) Instrinsic Jitter Filtered Table 11. C1.5 (1.544MHz) Instrinsic Jitter Filtered
Sym
Descr ip t ion Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter)
Test C on d it ion s*
Min
Typ
Ma x 0.015 0.010
Un it s UIpp UIpp UIpp UIpp
1-12, 19-22, 27 Instrinsic Jitter (8kHz to 40kHz Filter) Instrinsic Jitter (10Hz to 8kHz Filter)
* Refer to the Test Conditions on Page 24 for details.
0.010 0.005
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C2 (2.048MHz) Instrinsic Jitter Filtered Table 12. C2 (2.048MHz) Instrinsic Jitter Filtered
Sym
Descr ip t ion Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter)
Test C on d it ion s*
Min
Typ
Ma x 0.015 0.010
Un it s UIpp UIpp UIpp UIpp
1-12, 19-22, 28 Instrinsic Jitter (8kHz to 40kHz Filter) Instrinsic Jitter (10Hz to 8kHz Filter)
* Refer to the Test Conditions on Page 24 for details.
0.010 0.005
8kHz Input to 8kHz Output Jitter Transfer Table 13. 8kHz Input to 8kHz Output Jitter Transfer
Sym Descr ip t ion Jitter Attenuation for 1Hz with 0.01UIpp Input Jitter Attenuation for 1Hz with 0.54UIpp Input Jitter Attenuation for 10Hz with 0.10UIpp Input Jitter Attenuation for 60Hz with 0.10UIpp Input Jitter Attenuation for 300Hz with 0.10UIpp Input Jitter Attenuation for 3600Hz with 0.005UIpp Input Test C on d it ion s* Min 0 6 12 1, 4, 7-12, 19, 20, 22, 26, 33 28 42 45 38 dB dB dB Typ Ma x 6 16 22 Un it s dB dB dB
* Refer to the Test Conditions on Page 24 for details.
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1.544MHz Input to 1.544MHz Output Jitter Transfer Table 14. 1.544MHz Input to 1.544MHz Output Jitter Transfer
Sym Descr ip t ion Jitter Attenuation for 1Hz with 20UIpp Input Jitter Attenuation for 1Hz with 104UIpp Input Jitter Attenuation for 10Hz with 20UIpp Input Jitter Attenuation for 60Hz with 20UIpp Input Jitter Attenuation for 300Hz with 20UIpp Input Jitter Attenuation for 10kHz with 0.3UIpp Input Jitter Attenuation for 100kHz with 0.3UIpp Input 1, 5, 7-12, 19, 20, 22, 27, 33 Test C on d it ion s* Min 0 6 12 28 42 45 45 Typ Ma x 6 16 22 38 Un it s dB dB dB dB dB dB dB
* Refer to the Test Conditions on Page 24 for details.
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2.048MHz Input to 2.048MHz Output Jitter Transfer Table 15. 2.048MHz Input to 2.048MHz Output Jitter Transfer
Sym Descr ip t ion Test C on d it ion s* 1,6,7-12,19,20,22,28,33 Jitter at Output for 1Hz 3.00UIpp Input 1,6,7-12,19,20,22,28,34 1,6,7-12,19,20,22,28,33 Jitter at Output for 3Hz 2.33UIpp Input 1,6,7-12,19,20,22,28,34 1,6,7-12,19,20,22,28,33 Jitter at Output for 5Hz 2.07UIpp Input 1,6,7-12,19,20,22,28,34 1,6,7-12,19,20,22,28,33 Jitter at Output for 10Hz 1.76UIpp Input 1,6,7-12,19,20,22,28,34 Jitter at Output for 100Hz 1.50UIpp Input 1,6,7-12,19,20,22,28,33 1,6,7-12,19,20,22,28,34 1,6,7-12,19,20,22,28,33 1,6,7-12,19,20,22,28,34 1,6,7-12,19,20,22,28,33 1,6,7-12,19,20,22,28,34 0.10 0.06 0.05 0.04 0.03 0.04 0.02 UIpp UIpp UIpp UIpp UIpp UIpp UIpp 0.10 0.40 UIpp UIpp 0.10 0.80 UIpp UIpp 0.09 1.3 UIpp UIpp Min Typ Ma x 2.9 Un it s UIpp
Jitter at Output for 2400Hz 1.50UIpp Input
Jitter at Output for 100kHz 0.20UIpp Input
* Refer to the Test Conditions on Page 24 for details.
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8kHz Input Jitter Tolerance Table 16. 8kHz Input Jitter Tolerance
Sym Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 3600Hz Input 1, 4, 7-12, 19, 20, 22-24, 26 Test C on d it ion s* Min 0.80 0.70 0.60 0.20 0.15 0.08 0.02 0.01 Typ Ma x Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
* Refer to the Test Conditions on Page 24 for details.
1.544MHz Input Jitter Tolerance Table 17. 1.544MHz Input Jitter Tolerance
Sym Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 10kHz Input Jitter Tolerance for 100kHz Input 1, 5, 7-12, 19, 20, 22-24, 27 Test C on d it ion s* Min 150 140 130 35 25 15 4 1 0.5 Typ Ma x Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
* Refer to the Test Conditions on Page 24 for details.
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2.048MHz Input Jitter Tolerance Table 18. 2.048MHz Input Jitter Tolerance
Sym
Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 10kHz Input Jitter Tolerance for 100kHz Input
Test C on d it ion s*
Min 150 140 130 50
Typ
Ma x
Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
1, 6, 7-12, 19, 20, 22-24, 28
40 20 5 1 1
* Refer to the Test Conditions on Page 24 for details.
OSCi 20MHz Master Clock Input Table 19. OSCi 20MHz Master Clock Input
Sym Descr ip t ion Test C on d it ion s* 13, 16 Tolerance 14, 17 15, 18 Duty Cycle Rise Time Fall Time Min 0 -32 -100 40 Typ Ma x 0 +32 +100 60 10 10 Un it s ppm ppm ppm % ns ns
* Refer to the Test Conditions on Page 24 for details.
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Notes: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Supply voltage and operation temperature are as per Recommended Operating Conditions. 3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.
Test Conditions: 1. Normal State selected. 2. Auto-Holdover State. 3. Freerun State selected. 4. 8kHz frequency source selected. 5. 1.544MHz frequency source selected. 6. 2.048MHz frequency source selected. 7. Master clock input OSCi at 20MHz 0ppm. 8. Master clock input OSCi at 20MHz 32ppm. 9. Master clock input OSCi at 20MHz 100ppm. 10. Reference input at 0ppm. 11. Reference input at 32ppm. 12. Reference input at 100ppm. 13. For Freerun State of 0ppm. 14. For Freerun State of 32ppm. 15. For Freerun State of 100ppm. 16. For capture range of 230ppm. 17. For capture range of 198ppm. 18. For capture range of 130ppm. 19. 25pF capacitive load. 20. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 21. Jitter on reference input is less than 7ns p-p. 22. Applied jitter is sinusoidal. 23. Minimum applied input jitter magnitude to regain synchronization. 24. Loss of synchronization is obtained at slightly higher input jitter amplitudes. 25. Within 10 ms of the state or input change 26. 1UIpp = 125s for 8kHz signals. 27. 1UIpp = 648ns for 1.544MHz signals. 28. 1UIpp = 488ns for 2.048MHz signals. 29. 1UIpp = 323ns for 3.088MHz signals. 30. 1UIpp = 244ns for 4.096MHz signals. 31. 1UIpp = 122ns for 8.192MHz signals. 32. 1UIpp = 61ns for 16.384MHz signals. 33. No filter. 34. 40Hz to 100kHz bandpass filter. 35. With respect to reference input signal frequency. 36. After a RST. 37. Master clock duty cycle 40% to 60%. 38. Prior to Auto-Holdover State, device was in Normal State and phase-locked.
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Mechanical Specifications
Figure 11. 28-pin PLCC
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Data Sheet PT7A4401C T1/E1 System Synchronizer
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Ordering Information
Table 20. Ordering Information
Pa r t Nu mb er PT7A4401CJ
Pa ck a ge 28-Pin PLCC
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Notes
Pericom Technology Inc.
Email: support@pti.com.cn China: Asia Pacific: U.S.A.: Web-Site: www.pti.com.cn, www.pti-ic.com No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
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